[Gllug] Laptops?

Chris Bell chrisbell at overview.demon.co.uk
Wed Oct 29 20:26:47 UTC 2003

On Wed 29 Oct, Richard Jones wrote:

> The G4 processors are clocked pretty slow (typically under 1 GHz,
> compared to >2.5 GHz to the latest Intel laptops). Now my
> understanding was that the G4 was a RISC-ish processor, and so should
> be able to do fewer operations per cycle than the CISC-ish x86, and
> thus ought to be clocked considerably _higher_ and not lower. Now I
> assume that these Apple machines aren't actually really slow, so how
> does this work? Are they very superscalar? Vector architecture? Does
> the graphics architecture compensate for really slow main CPU?

   A simple basic process may require several 32-bit instructions to input
the data, perform an operation, and save the result to the required
destination.  A decision may be required based on a test performed on this
result, perhaps involving a jump to another part of the programme rather
than continuing with the next step in the sequence. A typical example would
involve inputting two data words, then entering a loop to compare the data
words, decide whether to continue with the next step or jump back, perform
an operation, and re-test. Research undertaken in the 1980's showed that a
small minority of commands were used repeatedly for the majority of the
time, so the best route was to make these simple commands as efficient as

   "CISC processors" (if there are any real ones) are supposed to be able to
perform a huge number of different processes, each one with its own binary
reference number. The total number of bits required to specify a command and
input the data may require several 32-bit words, so CISC processors tend to
have a very long pipeline, but the pipeline must be re-loaded every time
there is a jump to another part of the programme.

   RISC processors perform a limited number of processes, but there is
sufficient space left in a 32-bit command word to add some additional
options. RISC chips based on the ARM series use the spare space to provide
some carefully selected options designed to reduce the number of 32-bit
command words and speed simple loops similar to the example above. A typical
single command step would perform a test and, according to the result,
either proceed to the next step or jump back a small number of programme
steps. The process requires fewer programme steps and clock cycles, and
there is no real need for a very long pipeline. More complex operations need
to be held in libraries, but they are compact because there are relatively
few steps. Other advantages are that the processor chip can be small and
efficient, with fewer timing problems across the chip.

Chris Bell

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