[Gllug] Programming for performance on Linux

[Nix]

On 17 May 2010, general outgrape:

> Nix wrote:
>> On 14 May 2010, general said:
>>   
>>> I don't think L1 cache is shared, L2 cache can be though depending on
>>> the architecture. IIRC Intel Core 2 Duos have a shared L2 cache common
>>> to all cores
>>>     
>>
>> No, they have a shared *L3* cache common to all cores. L1/L2 is private
>> to a single core (though of course shared between hyperthreads on one
>> core).

This was inaccurate because I was (as usual) misled by Intel's
fantastically confusing CPU naming scheme. (I had to consult the heaps of
elaborate tables at Wikipedia to get this straight in my head again.)

>> e.g. on my hyperthreaded quad-core Nehalem:
>>
>> spindle:/sys/devices/system/cpu/cpu0/cache# for name in index*; do echo $(cat $name/type):L$(cat $name/level):$(cat $name/size):$(cat $name/shared_cpu_list); done
>> Data:L1:32K:0,4
>> Instruction:L1:32K:0,4
>> Unified:L2:256K:0,4
>> Unified:L3:8192K:0-7
>>
>> (this provides benefits for multithreading -- less cache bouncing if
>> running several threads of the same program -- and downsides for
>> multiprocessing -- the effective available cache shrinks as the number
>> of simultaneously running processes not sharing cache goes up.)
>
> Really?

No! :/

> Quoting from http://www.intel.com/products/processor/core2duo/index.htm
>> With an Intel® 
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Core~2 Duo processor you will get performance-rich
>> technologies, including up to 6MB of shared L2 cache, up to 1333 MHz
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>> Front Side Bus, plus these additional Intel® technologies built in: 

Different CPU. FSB -> not Nehalem -> shared L2 cache. Nehalems
(including the Core i7 et al, some of which were initially sold as Core
2 by some vendors even though Intel don't call them that, gee, thanks)
have a nonshared L2 cache and a shared L3.
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