[Gllug] Re: Dual core AMDs

[Richard Jones]

On Wed, Jul 13, 2005 at 04:42:23PM +0100, Christian Smith wrote:
> Ah, but it did save a branch instruction, which was at least 2 (3?) cycles
> per loop. There was non of this modern pipelining technology back then,
> you know(*).

Ah, but a common hack was to unroll the LDIR - writing it as a block
of LDI (IIRC?) instructions which a single jump at the end of the
block.  Actually, it was probably a DJNZ instruction at the end of the
block.

> (*) Actually, the Z80 did make a few instructions execute 1 cycle slower,
>     so that it could get the next instruction in flight, thus forming a
>     primitive 2 stage pipeline under some circumstances. Can't remember
>     the instructions, but they could have been some memory writes.

Rodney Zaks' "Programming the Z80" is the definitive reference on
this, and if only I could be bothered to reach over about 20 inches to
my right, I'd pull my old copy out and get the definitive answer.  As
it is, it's under a huge pile of books, so I'll go for the answer from
memory instead ...  The accumulator register wasn't part of the normal
register bank, and because of this it was possible to write directly
from the output of the ALU to the accumulator without going over the
data bus.  Thus you could fetch the next instruction from memory (an
operation which involved using the data bus) at the same time as
updating the A register with the result from the previous ALU op.
Thus just about any arithmetic op could be overlapped with the start
of the next instruction.

Rich.

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Richard Jones, CTO Merjis Ltd.
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