[Gllug] Re: Dual core AMDs

[Chris Bell]

On Tue 12 Jul, Nix wrote:
> 
> On Tue, 12 Jul 2005, Chris Bell moaned:
> >    That I do understand, but I thought there was a big difference between
> > the pipeline and an on-chip cache. Both the Strong ARM and the Crusoe had a
> > cache large enough to house most of a programming language as well as data,
> 
> What does that mean?
> 
   I understand that the Crusoe chips could could hold almost an entire
kernel on chip. The Strong ARM chips ran languages such as BASIC much faster
than expected because they were also loaded into cache.


> 
> >    Some CISC chips are only efficient when they are doing work which
> > involves steady progress through a long pipeline. Any looping or jumping to
> > other locations often involves clearing the pipeline and is expensive, even
> > when the new data is held in the on-chip cache.
> 
> Much of this is true of *all* chips. Even RISC chips need long pipelines
> these days, relative RAM/CPU speeds being what they are. (In fact,
> they're even more dependent on pipelines and sensitive to pipeline
> stalls than are CISC chips.)
> 
   I understood that the ARM chips are designed to do simple repetitive
routines very rapidly, have a reasonably large on-chip cache, but a
relatively short pipeline. CISC chips are supposed to be able to perform
complex tasks, but too much of their real work involves simple repetitive
instructions, for which they are not optimised.

-- 
Chris Bell

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