[Gllug] Re: Dual core AMDs
nix at esperi.org.uk
Tue Jul 12 10:14:53 UTC 2005
On Tue, 12 Jul 2005, Chris Bell moaned:
> That I do understand, but I thought there was a big difference between
> the pipeline and an on-chip cache. Both the Strong ARM and the Crusoe had a
> cache large enough to house most of a programming language as well as data,
What does that mean?
- Most of the language runtime, well, that really depends on the language.
C++ and C have small runtimes --- if you ignore glibc, which might fit
in 2Mb caches, I suppose; as for Java, no chance. Ada, maybe.
- Most of the compiler, no chance.
- Most of the language spec text (!) no chance except for a very few
languages. (I really doubt this is what you mean; there's little call for
holding language specs in L1 cache ;) )
> Some CISC chips are only efficient when they are doing work which
> involves steady progress through a long pipeline. Any looping or jumping to
> other locations often involves clearing the pipeline and is expensive, even
> when the new data is held in the on-chip cache.
Much of this is true of *all* chips. Even RISC chips need long pipelines
these days, relative RAM/CPU speeds being what they are. (In fact,
they're even more dependent on pipelines and sensitive to pipeline
stalls than are CISC chips.)
`But of course, GR is the very best relativity for the masses.'
--- Wayne Throop
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