[Gllug] Re: Dual core AMDs

[Chris Bell]

On Wed 13 Jul, Christopher Hunter wrote:
> On Tuesday 12 Jul 2005 21:22, Rich Walker wrote:
> 
> > The PIC is *not* a RISC CPU!
> 
> I would strongly argue (probably wrongly 8-) ) that the minimal instruction 
> set of the smaller PICs is seriously "reduced" - certainly when compared to 
> something like the Z80 series of processors (which I did almost all my early 
> embedded stuff on).
> 
> Chris
> 

   The whole point about the ARM chips is that there are fewer basic
instructions, so they are selected using fewer data bits, but instruction
words are long enough to contain some options (sources, destinations,
conditional jumps, etc) as well as the main instructions. This results in
very compact code, requiring the minimum number of clock pulses. It is not
simply a reduced instruction set.
   CISC chips provide a large choice of instructions, but more data bits are
required to select the correct one, with less compact code. The chips must
be physically large to provide the instructions in hardware, which increases
transit times, perhaps mitigated by more powerful drivers which then get
hotter. This would be tolerable if the additional instructions and related
hardware do not just sit unused.

   On another point, I am intrigued by your need to add a Reply-To: "NOSPAM"
line. My system is happy to reply to each and every address, but only the
first address is normally visible in the To: box.

-- 
Chris Bell

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