Dual core AMDs (was Re: [Gllug] Recording Ogg streams?)

[Chris Bell]

On Tue 12 Jul, John Hearns wrote:
> 

> The RISC/CISC wars are over, and I think the answer is that CISC has
> won, with elements of RISC, as you say.

   Yet I heard that Intel were very keen to take control of the old DEC
plant that produced the original Strong ARM chips. Am I being cynical when I
suggest that it is more of a PR/marketing decision, feel the clock speed,
never mind the quality?

> 
> Large caches are needed, because there is a lot of instruction prefetch
> and also speculative prefetch.
> 

   That I do understand, but I thought there was a big difference between
the pipeline and an on-chip cache. Both the Strong ARM and the Crusoe had a
cache large enough to house most of a programming language as well as data,
but the range of commands offered by ARM RISC chips was carefully selected
so that a complete command plus any required data would fit into the minimum
number of clock pulses and gave efficient testing and looping, with the next
instruction often ready waiting for the looping to finish without clearing
the short pipeline.
   Some CISC chips are only efficient when they are doing work which
involves steady progress through a long pipeline. Any looping or jumping to
other locations often involves clearing the pipeline and is expensive, even
when the new data is held in the on-chip cache.


-- 
Chris Bell

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